Electronic matrix arrays find considerable application in X-ray imagers and active matrix liquid crystal displays (AMLCDs). Such AMLCDs and X-ray imagers generally include X and Y (or row and column) address lines which are horizontally and vertically spaced apart and cross at an angle to one another thereby forming a plurality of crossover points. Associated with each crossover point is an element (e.g. pixel) to be selectively addressed. These elements in many instances are liquid crystal display pixels or alternatively the memory cells of an electronically adjustable memory array or X-ray imaging array.
Typically, a switching or isolation device such as a diode or thin film transistor (TFT) is associated with each array element or pixel. The isolation devices permit the individual pixels to be selectively addressed by the application of suitable potentials between respective pairs of the X and Y address lines. Thus, the TFTs act as switching elements for energizing or otherwise addressing corresponding pixel electrodes.
Amorphous silicon (a-Si) TFTs have found wide usage for isolation devices in liquid crystal display (LCD) arrays and X-ray imagers. Structurally, TFTs generally include substantially co-planar source and drain electrodes, a thin film semiconductor material (e.g. a-Si) disposed between the source and drain electrodes, and a gate electrode in proximity to the semiconductor but electrically insulated therefrom by a gate insulator. In LCDs, current flow through a TFT between the source and drain is controlled by the application of voltage to the gate electrode. The voltage to the gate electrode produces an electric field which accumulates a charged is region near the semiconductor-gate insulator interface. This charged region forms a current conducting channel in the semiconductor through which current is conducted. Thus, by controlling the voltage to the gate and drain electrodes, pixels may be switched on and off in a known manner.
Herein, "drain" electrodes are those which are in communication with a drain address line and "source" electrodes are those that are in communication with the pixel electrodes through vias in the insulating layers.
It is old and well-known to make TFT arrays wherein address lines and overlapping pixel electrodes are insulated from one another by an insulating layer. For example, see U.S. Pat. Nos. 5,641,974; 5,055,899; 5,182,620; 5,414,547; 5,426,523; 5,446,562; 5,453,857; and 5,457,553, the disclosures of which are incorporated herein by reference.
Unfortunately, when certain prior art pixel electrodes are arranged so as to overlap the address lines (e.g. U.S. Pat. No. 5,003,356), an undesirably high parasitic capacitance results in the overlap areas between the pixel electrodes and the address lines. In overlap areas, the pixel electrode forms a capacitor in combination with the overlapped address lines. The resulting parasitic capacitance C.sub.PL between the pixel electrode and the address line in the area of overlap is defined as follows: EQU C.sub.PL =(.epsilon..multidot..epsilon..sub.0 .multidot.A).div.d
where ".epsilon." is the dielectric constant of the insulating layer, ".epsilon..sub.0 " is a constant value of about 8.85.times.10.sup.-14 F/cm, "A" is the area of the resulting capacitor in the area of overlap, and "d" is the thickness of the insulating layer in the area of overlap. PA1 a substrate; PA1 an array of thin film transistors (TFTs) disposed on the substrate, the array of TFTs including a plurality of address lines connected to the TFTs; PA1 an array of substantially transparent electrodes disposed on the first substrate, a plurality of the electrodes in the array of electrodes overlapping at least one of the address lines; PA1 an organic photo-imageable insulating layer having a dielectric constant less than about 4.0 disposed on the substrate between the address lines and the electrodes at least in areas of overlap and areas adjacent source electrodes of the TFTs; PA1 an intermediate protective insulating layer disposed between the TFTs and the photo-imageable insulating layer so as to prevent the organic photo-imageable insulating layer from directly contacting semiconductor material in channels of the TFTs thereby reducing potential shifts of threshold voltage and subthreshold swings in the TFTs; and PA1 the photo-imageable insulating layer and the intermediate protective layer each having a plurality of contact vias defined therein, wherein the electrodes are in electrical communication with corresponding TFT source electrodes through the contact vias defined in the insulating layers. PA1 a first substrate; PA1 a liquid crystal layer; PA1 an array of substantially transparent pixel electrodes on the first substrate for permitting image data to be displayed to a viewer; PA1 a plurality of gatelines and TFT gate electrodes on the first substrate; PA1 a semiconductor layer patterned so as to remain in an array of TFT areas; PA1 a source and drain electrode in each TFT area on the first substrate, a TFT channel being defined between a corresponding source and drain electrodes of each TFT, thereby forming an array of TFTs on the first substrate; PA1 drain lines connected to the drain electrodes; PA1 wherein a plurality of the pixel electrodes overlap at least one of a gateline and a drain line thereby increasing the pixel aperture ratio of the display; PA1 a substantially transparent photo-imageable insulating layer having a dielectric constant less than about 4.0, the photo-imageable insulating layer being disposed on the first substrate between (i) the pixel electrodes and (ii) the TFTs and the overlapped lines so as to insulate the pixel electrodes from the overlapped lines and the TFTs; and PA1 an intermediate insulating layer disposed between the photo-imageable insulating layer and the TFTs so as to prevent the photo-imageable insulating layer from directly contacting TFT portions which the photo-imageable insulating layer overlap. PA1 an array of TFTs on a substrate, the TFTs being connected to a corresponding array of electrodes; PA1 row and column address lines on the substrate for addressing the TFTs; PA1 organic photo-imageable insulating means having a dielectric constant less than about 4.0 disposed between the electrodes and the address lines so as to reduce crosstalk and permit the insulating means to be photo-imaged; and PA1 an intermediate protective insulating layer disposed between the photo-imageable insulating means and the TFTs so as to prevent the insulating means from contacting semiconductor material of the TFTs.
When a thin profile silicon nitride insulator is used as in U.S. Pat. No. 5,003,356, the resulting parasitic capacitance created by the overlap is undesirably high thereby resulting in capacitive crosstalk in the LCD. The dielectric constant of silicon nitride is well over 5.0 (typically from about 6.4 to 7.2). Such crosstalk results when the signal voltage intended to be on a particular pixel is not there. Thus, when C.sub.PL is too high, the voltage on the pixel is either higher or lower than intended depending upon how much voltage the other pixels on the signal address line receive. In other words, the pixel is no longer satisfactorily isolated when C.sub.PL is too high. In view of the above, there exists a need in the art for an LCD (and/or X-ray imager) having both an increased aperture ratio as well as reduced capacitive crosstalk in overlap areas so as to simultaneously and properly isolate each pixel and increase the pixel opening sizes.
Further with respect to the '356 patent, for example, its disclosure does not appreciate the importance of the dielectric constant .epsilon. of the insulating layer. While referencing numerous materials including silicon nitride and SiO.sub.2, which may be used for the insulating layer, the '356 patent does not discuss either the dielectric constant values of these materials or their importance in helping reduce C.sub.PL in overlap areas. When .epsilon. of the insulating layer is too high, capacitive crosstalk results.
Recently, organic polymer films have been applied to TFT-LCDs as an insulating layer between address lines and pixel electrodes in high aperture applications. For example, see commonly owned U.S. Pat. No. 5,641,974. There has been increasing concern as to how such polymers affect back-channel-etch TFT performance and reliability. It has been found that both threshold voltage and sub-threshold swing can be degraded by acrylic or black resin insulating layers, as compared to silicon nitride, for example. In addition, a high off-current shoulder in sub-threshold regions has been found after negative gate voltage stress on acrylic passivated TFTs. The mechanism behind such degradation is believed to be that fixed charge and defect states are created at the interface between the organic insulating layer and the a-Si TFT layer.
As the performance of LCDs and X-ray imagers is dependent upon TFT characteristics in both the off-state and sub-threshold regions, the below-referenced invention is an improvement over the disclosure of the commonly owned '974 patent in an effort to improve TFT characteristics and performance.
It is apparent from the above that there exists a need in the art for an improved TFT array and/or resulting LCD (or X-ray imager) having an increased pixel aperture ratio, good TFT performance in all regions, and little capacitive crosstalk. Such an LCD or X-ray imager should be made with as few steps as possible.
It is a purpose of this invention to fulfill the above-described needs in the art, as well as other needs which will become apparent to the skilled artisan from the following detailed description of this invention.